Reading for Wednesday, October 18

  1. Jonathan Rose, Robert Francis, David Lewis, and Paul Chow. Architecture of Field-Programmable Gate Arrays: The Effect of Logic Block Functionality on Area Efficiency. IEEE Journal of Solid-State Circuits, 25(5):1217--1225, October 1990.

Supplemental Reading

  1. André DeHon, Reconfigurable Architectures for General-Purpose Computing. AI Technical Report 1586, MIT Artificial Intelligence Laboratory, 545 Technology Sq., Cambridge, MA 02139, pages 35-41, October 1996. [PS for pp. 35-41], [HTML for Chapter 4], [Full Document].
  2. S. Singh, Jonathan Rose, Paul Chow, and David Lewis. The Effect of Logic Block Architecture on FPGA Performance. IEEE Journal of Solid-State Circuits, 27(3):281--287, March 1992.
  3. Chuck Hastings, When is a Memory Not a Memory, In Proceedings of the Electro/87 Mini/Micro Northeast, page 1132 ff. (4/5/1-18), 1987.
  4. Stephen D. Brown, Robert J. Francis, Jonathan Rose, and Zvonko G. Vranesic. Field-Programmable Gate Arrays. Kluwer Academic Publishers, 101 Philip Drive, Assinippi Park, Norwell, Massachusetts, 02061 USA, 1992.
Course Calendar
CS184a: Computer Architecture