Supplemental Reading

  1. Jonathan Rose and Stephen Brown, The Effect of Switch Box Flexibility on Routability of Field Programmable Gate Arrays. In Proceedings of the 1990 Custom Integrated Circuits Conference, p. 27.5.1--4, 1990.
  2. Yu-Liang Wu, Shuji Tsukiyama, and Malgorzata Marek-Sadowska, Graph Based Analysis of 2-D FPGA Routing. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 15(1):33--44, January 1996.
  3. Yu-Liang Wu, Douglas Chang, Malgorzata Marek-Sadowska, and Shiji Tsukiyama, Not Necessarily More Switches More Routability. In Proceesings of the 1996 Asia Pacific Design Automation Conference, 1996.
  4. Jonathan Rose and Stephen Brown. Flexibility of Interconnection Structures for Field-Programmable Gate Arrays. IEEE Journal of Solid-State Circuits, 26(3):277--282, March 1991.
  5. Yao-Wen Chang and D. F. Wong and C. K. Wong. Universal Switch-Module Design for Symmetric-Array-Based FPGAs. In Proceedings of the 1996 International Symposium on Field-Programmable Gate Arrays, pages 80--86. ACM/SIGDA, February, 1996.
  6. Muhammad Khellah, Stephen Brown, and Zvonko Vranesic, "Minimizing Interconnection Delays in Array-based FPGAs," In Proceedings of the 1994 Custom Integrated Circuits Conference, pages 181-184, San Diego CA, May 1994. [PS]
  7. Stephen D. Brown, Robert J. Francis, Jonathan Rose, and Zvonko G. Vranesic. Field-Programmable Gate Arrays. Kluwer Academic Publishers, 101 Philip Drive, Assinippi Park, Norwell, Massachusetts, 02061 USA, 1992.
  8. André DeHon. Entropy, Counting, and Programmable Interconnect. (Shorter version in FPGA'96). [HTML] [TR PS] n.b. The switching requirements for the m choose k switching block is detailed in the appendix in this TR.
  9. Aditya A. Agarwal and David Lewis. Routing Architectures for Hierarchical Field Programmable Gate Arrays. In Proceedings 1994 IEEE International Conference on Computer Design, pages 475--478. IEEE, October 1994.
  10. Vi Cuong Chan and David M. Lewis. Area-Speed Tradeoffs for Hierarchical Field-Programmable Gate Arrays. In Proceedings of the 1996 International Symposium on Field-Programmable Gate Arrays, pages 51--57. ACM/SIGDA, February, 1996.
  11. Sandeep Bhatt and Frank Thomson Leighton. A Framework for Solving VLSI Graph Layout Problems. In Journal of Computer System Sciences v28p300-343, 1984.
  12. Ronald I. Greenberg and Charles E. Leiserson. A Compact Layout for the Three-Dimensional Tree of Meshes. In Applied Math Letters v1n2p171--176, 1988.
  13. André DeHon. Compact, Multilayer Layout for Butterfly Fat-Tree. In Twelfth Annual ACM Symposium on Parallel Algorithms and Architectures (SPAA 2000), pages 206--215, July 9-12, 2000. [abstract, paper links].
  14. André DeHon. Delays in VLSI Structures. Lectures in UCB CS294-7 (Reconfigurable Computing), Spring 1997. [http://www.cs.berkeley.edu/~amd/CS294S97/notes/day14/day14.html]
  15. André DeHon, Reconfigurable Architectures for General-Purpose Computing. AI Technical Report 1586, MIT Artificial Intelligence Laboratory, 545 Technology Sq., Cambridge, MA 02139, pages 63--88, October 1996. [PS for pp. 63-88], [HTML for Chapter 7], [Full Document].

Course Calendar
CS184a: Computer Architecture