Reading for Wednesday, November 1, and Monday, November 6
- André DeHon. Balancing Interconnect and Computation in a
Reconfigurable Computing Array (or, why you don't really want 100% LUT
utilization). In Proceedings of the International Symposium on Field
Programmable Gate Arrays, pages 125--134, February 1999.
[abstract,
paper, and slide links].
Supplemental Reading
- Russell Tessier and Heather Giza. Balancing Logic Utilization and Area Efficiency in FPGAs.
In Conference on Field Programmable Logic and Applications (FPL '2000),
pages 535--544, August 28--30, 2000.
Course Calendar
CS184a: Computer Architecture